Design Verification Engineer

Company: Meta Inc
Location: Cheyenne
Posted on: March 20, 2023

Job Description:

Summary:
Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta's Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs.
Required Skills:
Design Verification Engineer Responsibilities:

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  Work with researchers and architects defining verification methodologies for each of the different core IP.
  
  
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  Define and track detailed test plans for the different modules and top levels.
  
  
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  Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
  
  
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  Keep track of coverage metrics and bugs encountered and fixed.
  
  
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  Implement self-testing directed and random tests.
  
  
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  Support post silicon bring up and debug activities.
  
  
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  Ability to communicate clearly.
  
  
  Minimum Qualifications:
  Minimum Qualifications:
  
  
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  2+ years of System Verilog OVM/UVM DV experience.
  
  
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  Knowledge of Python, Perl, shell scripting.
  
  
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  Knowledge with assertions (SVA) or others.
  
  
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  Knowledge of digital ASICs design flows.
  
  
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  Bachelors degree in Electrical Engineering or Computer Science or equivalent experience.
  
  
  Preferred Qualifications:
  Preferred Qualifications:
  
  
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  C, C++ coding, debugging experience.
  
  
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  Experience as a digital design engineer.
  
  
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  Experience with low power design.
  
  
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  FPGA implementation and debug experience.
  
  
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  Experience in verification of numerical compute based designs.
  
  
  Public Compensation:
  $136,000/year to $195,000/year + bonus + equity + benefits
  Industry: Internet
  Equal Opportunity:
  Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. We may use your information to maintain the safety and security of Meta, its employees, and others as required or permitted by law. You may view Meta's Pay Transparency Policy, Equal Employment Opportunity is the Law notice, and Notice to Applicants for Employment and Employees by clicking on their corresponding links. Additionally, Meta participates in the E-Verify program in certain locations, as required by law

Keywords: Meta Inc, Cheyenne , Design Verification Engineer, Engineering , Cheyenne, Wyoming